pcb try
This commit is contained in:
parent
cb938871b8
commit
c7090483cd
4 changed files with 1962 additions and 934 deletions
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@ -7,10 +7,10 @@
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* D0 - MOSFET Fan
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* D1, D2 - I2C
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* D3 - DHT11
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* D4 - analog soil moisture (set HIGH to read value)
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* D5 - MOSFET Grow LED, PWM
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* D6 - MOSFET Pump
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* D7 - waterlevel (set HIGH to read value)
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* D8 - analog soil moisture (set HIGH to read value)
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* A0 - analog input for soil moisture and waterlevel readings
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*
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* D4 and D7 cannot be HIGH at the same time!
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@ -28,10 +28,10 @@ uint8_t PINfan = D0;
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// If D3 is pulled to LOW, boot fails
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uint8_t PINdht = D3;
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// D4 is HIGH at boot, boot fail if pulled to LOW
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uint8_t PINsoilmoisture = D4;
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uint8_t PINled = D5; //
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uint8_t PINpump = D6;
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uint8_t PINwaterlevel = D7;
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uint8_t PINsoilmoisture = D8;
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uint8_t PINanalog = A0;
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#define WIRE Wire
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File diff suppressed because it is too large
Load diff
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@ -6,14 +6,14 @@
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"apply_defaults_to_fp_fields": false,
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"apply_defaults_to_fp_shapes": false,
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"apply_defaults_to_fp_text": false,
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"board_outline_line_width": 0.049999999999999996,
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"copper_line_width": 0.19999999999999998,
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"board_outline_line_width": 0.05,
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"copper_line_width": 0.2,
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"copper_text_italic": false,
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"copper_text_size_h": 1.5,
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"copper_text_size_v": 1.5,
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"copper_text_thickness": 0.3,
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"copper_text_upright": false,
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"courtyard_line_width": 0.049999999999999996,
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"courtyard_line_width": 0.05,
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"dimension_precision": 4,
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"dimension_units": 3,
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"dimensions": {
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@ -24,13 +24,13 @@
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"text_position": 0,
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"units_format": 1
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},
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"fab_line_width": 0.09999999999999999,
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"fab_line_width": 0.1,
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"fab_text_italic": false,
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"fab_text_size_h": 1.0,
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"fab_text_size_v": 1.0,
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"fab_text_thickness": 0.15,
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"fab_text_upright": false,
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"other_line_width": 0.09999999999999999,
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"other_line_width": 0.1,
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"other_text_italic": false,
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"other_text_size_h": 1.0,
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"other_text_size_v": 1.0,
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@ -41,17 +41,23 @@
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"height": 1.524,
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"width": 1.524
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},
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"silk_line_width": 0.09999999999999999,
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"silk_line_width": 0.1,
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"silk_text_italic": false,
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"silk_text_size_h": 1.0,
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"silk_text_size_v": 1.0,
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"silk_text_thickness": 0.09999999999999999,
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"silk_text_thickness": 0.1,
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"silk_text_upright": false,
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"zones": {
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"min_clearance": 0.5
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"min_clearance": 0.0
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}
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},
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"diff_pair_dimensions": [],
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"diff_pair_dimensions": [
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{
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"gap": 0.0,
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"via_gap": 0.0,
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"width": 0.0
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}
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],
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"drc_exclusions": [],
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"meta": {
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"version": 2
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@ -114,15 +120,15 @@
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"min_copper_edge_clearance": 0.5,
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"min_hole_clearance": 0.25,
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"min_hole_to_hole": 0.25,
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"min_microvia_diameter": 0.19999999999999998,
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"min_microvia_drill": 0.09999999999999999,
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"min_microvia_diameter": 0.2,
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"min_microvia_drill": 0.1,
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"min_resolved_spokes": 2,
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"min_silk_clearance": 0.0,
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"min_text_height": 0.7999999999999999,
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"min_text_height": 0.8,
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"min_text_thickness": 0.08,
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"min_through_hole_diameter": 0.3,
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"min_track_width": 0.0,
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"min_via_annular_width": 0.09999999999999999,
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"min_via_annular_width": 0.1,
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"min_via_diameter": 0.5,
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"solder_mask_to_copper_clearance": 0.0,
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"use_height_for_length_calcs": true
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@ -170,7 +176,9 @@
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"td_width_to_size_filter_ratio": 0.9
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}
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],
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"track_widths": [],
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"track_widths": [
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0.0
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],
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"tuning_pattern_settings": {
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"diff_pair_defaults": {
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"corner_radius_percentage": 80,
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@ -197,7 +205,12 @@
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"spacing": 0.6
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}
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},
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"via_dimensions": [],
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"via_dimensions": [
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{
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"diameter": 0.0,
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"drill": 0.0
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}
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],
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"zones_allow_external_fillets": false
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},
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"ipc2581": {
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@ -437,7 +450,7 @@
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"classes": [
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{
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"bus_width": 12,
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"clearance": 0.2,
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"clearance": 0.3,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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@ -447,7 +460,7 @@
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"name": "Default",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.2,
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"track_width": 0.6,
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"via_diameter": 0.6,
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"via_drill": 0.3,
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"wire_width": 6
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@ -2725,6 +2725,16 @@
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)
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(uuid "61c21a51-7d03-4605-b834-349037b97794")
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)
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(wire
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(pts
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(xy 125.73 77.47) (xy 113.03 77.47)
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)
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(stroke
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(width 0)
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(type default)
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)
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(uuid "63954134-5b45-407c-8346-bfa6a006c28b")
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)
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(wire
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(pts
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(xy 68.58 128.27) (xy 76.2 128.27)
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@ -2825,16 +2835,6 @@
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)
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(uuid "81ac692e-5ed3-41d8-aba1-339ce39a462e")
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)
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(wire
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(pts
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(xy 125.73 67.31) (xy 125.73 162.56)
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)
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(stroke
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(width 0)
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(type default)
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)
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(uuid "82bf73e6-1e06-4d48-b8e8-0eb464281ae0")
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)
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(wire
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(pts
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(xy 196.85 54.61) (xy 191.77 54.61)
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@ -2885,6 +2885,16 @@
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)
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(uuid "89cf13a4-5e61-4bee-a27f-d02c293f7562")
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)
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(wire
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(pts
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(xy 125.73 162.56) (xy 125.73 77.47)
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)
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(stroke
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(width 0)
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(type default)
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)
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(uuid "91fa63b6-a31e-46f6-a64c-f23e34938d81")
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)
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(wire
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(pts
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(xy 193.04 49.53) (xy 193.04 62.23)
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@ -3295,16 +3305,6 @@
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)
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(uuid "ff7d6bc6-4b02-421e-8637-954dcc023e3a")
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)
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(wire
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(pts
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(xy 125.73 67.31) (xy 113.03 67.31)
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)
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(stroke
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(width 0)
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(type default)
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)
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(uuid "ff95b020-31d3-4ab4-b0cf-084e390728d3")
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)
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(wire
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(pts
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(xy 113.03 62.23) (xy 193.04 62.23)
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@ -3385,7 +3385,7 @@
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)
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(uuid "a1650987-1fd0-4684-839d-80d4778c0e67")
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)
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(text "Pin D4"
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(text "Pin D8"
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(exclude_from_sim no)
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(at 121.666 161.29 0)
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(effects
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